RISC-V Development Board

FII-PRX100 Development Board ( ARTIX 100T, XC7A100T, RISC-V FPGA Developing Board)

FII-PRX100 Educational Platform Educational Plaform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Description

FII-PRX100 Educational Platform Educational Plaform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

FII-PRX100 Educational Platform Educational Plaform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Features:

  1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
  2. 3-stage pipeline architecture
  3. support machine mode only
  4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
  5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
  6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
  1. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
  2. 2 UART
  3. 3 QSPI
  4. I2C
  5. 3 PWM
  6. 10M/100M/1G ethernet
  7. Watchdog
  8. 32 GPIO
  9. 4 7-seg display interface
  10. External Serial Flash
  11. Debug Interfaces: JTAG
  12. 12-Bit ADC
  13. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
  14. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertor, QSPI flash, I2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO , hdmi transmitter and camera etc.

RISC-V IPCore user development Guide

This document is edited by Fraser Innovation Inc. Step by step introduce how to develop each RISC-V CPU RTL modules based on RISC-V ISA, Simulations and board verifications, software environment and details on C language development, debug and program

Artificial Intelligence

Voice collection, speech recognition
Image acquisition and image recognition, deep learning

IOT

FII-PRX100 Educational Plaform Product Features:

  • FPGA part:  XC7A100T-2FGG676I
  • 1MSPS On-chip:  yes
  • Logic Cells:  101440
  • Logic Slices: 15850
  • Flip-flops: 65200
  • Memory blocks(36K): 135
  • Memory block(Kb): 4860
  • Clock Management Tiles: 6
  • DSP Slices: 240

System Features:

  • ADC: On-chip analog-to-digital converter (XADC)
  • Super Sram? IS61WV25616 (2 slices ) 256K x 32bit
  • Spi Flash? serial flash (16M bytes)
  • JTAG:  jtag Programmable ports
  • Multifunction: used for other board  (For example: iMX226 camera board, or adv7612 Hdmi in board , etc)
  • Power Supply? 12V adapter source

Interaction and Sensory Devices:

  • 8 Switches
  • 7 Buttons (up , down, left, right, ok, menu, return)
  • 1 Reset button
  • 8 LEDs
  • 1 4-digit 7 segment display
  • 1 I2c interface (24c02 eeprom)
  • Expansion Connector:

  • 4 gpio connectors (compatible with digilent Pmod)
  • 2 MultiFunction connectors (connect with iMX226 board, or others?
  • Main Chips: xilinx (1.0mm pitch) XC7A100T_FGG676

Interaction and Sensory Devices

  • GPIO Interface  (16 ) 2×8 Standard 2.54mm connector (pin)
  • led output  (8 ) 0603 SMD
  • 8 switchs SMD
  • 7 buttons (Top, Bottom, left, right,center, top left (menu), top right (return)
  • i2c 24c02 smd soic
  • spi flash MX25L6433F 8-SOP (8M bytes)
  • usb2uart ft2232C/H (2 uart ) Or cp2102 (1  uart)
  • jtag 2×5 Standard 2.54mm connectors(pin)
  • eth 1G CAT5 Ethernet (rtl8111e)
  • sram IS61WV25616 (2 pieces ) 256K x 32bit
  • Digital tube 7seg (4) oasistek TOF-5421BMRL-N 
  • Hdmi out adv7511? hdmi_adv7511.SchDoc
  • Test Port? 1×6 Standard2.54mm Connectors ?pin?

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. A reduced instruction set computer, or RISC (/r?sk/), is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC). Various suggestions have been made regarding a precise definition of RISC, but the general concept is that such a computer has a small set of simple and general instructions, rather than a large set of complex and specialized instructions. Another common RISC trait is their load/store architecture, in which memory is accessed through specific instructions rather than as a part of most instructions.

The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

As of March 2019, version 2.2 of the user-space ISA is frozen, permitting most software development to proceed. The privileged ISA is available as draft version 1.10. A debug specification is available as a draft version 0.13.1

Commercial Companies of RISC-V

  • SiFive, a company established specifically for developing RISC-V hardware, has processor models released in 2017. These include a RISC-V SoCa quad-core, 64-bit system on a chip (SoC).
  • FII, Fraser Innovation Inc has developed RISC-V FPGA boards which includes Risc-V Development Board ( ARTIX 100T, XC7A100T, RISC-V FPGA Developing Board) and Altera risc-v SOPC AI Cyclone10 FPGA Board
  • Syntacore, a founding member of the RISC-V Foundation and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core. First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.
  • Andes Technology Corporation, a founding member of the RISC-V Foundation which joined the consortium in 2016, released its first two RISC-V cores in 2017. The cores, the N25 and NX25, come with a complete design ecosystems and a number of RISC-V partners. Andes is actively driving the development of RISC-V ecosystem and expects to release several new RISC-V products in 2018.
  • Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip’s RISC-V cores and other IP with UltraSoC’s debug, optimization and analytics.
  • Imperas has developed a family of fast processor models for the different subsets of RV32GC and RV64GC ISA variants that are part of the OVPsim instruction accurate simulator distributions used for embedded software development.
  • GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.
  • Hex Five announced general availability MultiZone Security – the first RISC-V trusted execution environment (TEE) using the standard RISC-V ISA and privileged mode extensions.
  • CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.
  • T-Head, a semiconductor business unit of Alibaba Group, has a commercial MCU, Scorpio, in production in 2019.
  • IAR Systems released the first version of IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions in the first version. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.
  • Western Digital, in February 2019 announced a 32-bit RISC-V core called SweRV. The SweRV features an In-Order 2-way superscalar and nine-stage pipeline design. WD plans to use SweRV based processors in their flash controllers and SSDs, and will release it open-source to third parties starting from Q1 2019.
  • Instant SoC by FPGA Cores generates RISC-V core, peripherals and memories directly from C++.