RISC-V FPGA Boards

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.

The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

As of March 2019, version 2.2 of the user-space ISA is frozen, permitting most software development to proceed. The privileged ISA is available as draft version 1.10. A debug specification is available as a draft version 0.13.1.

Risc-V Study Board
Risc-V FPGA Study Board

The FII-PRX100 RISC-V development board introduction

  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertor, QSPI flash, I2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO , hdmi transmitter and camera etc.

RISC-V IPCore user development Guide

This document is edited by Fraser Innovation Inc. Step by step introduce how to develop each RISC-V CPU RTL modules based on RISC-V ISA, Simulations and board verifications, software environment and details on C language development, debug and program

Artificial Intelligence

Voice collection, speech recognition
Image acquisition and image recognition, deep learning

IOT

FII-PRX100 Educational Plaform Product Features:

  • FPGA part:  XC7A100T-2FGG676I
  • 1MSPS On-chip:  yes
  • Logic Cells:  101440
  • Logic Slices: 15850
  • Flip-flops: 65200
  • Memory blocks(36K): 135
  • Memory block(Kb): 4860
  • Clock Management Tiles: 6
  • DSP Slices: 240

System Features:

  • ADC: On-chip analog-to-digital converter (XADC)
  • Super Sram? IS61WV25616 (2 slices ) 256K x 32bit
  • Spi Flash? serial flash (16M bytes)
  • JTAG:  jtag Programmable ports
  • Multifunction: used for other board  (For example: iMX226 camera board, or adv7612 Hdmi in board , etc)
  • Power Supply? 12V adapter source

Interaction and Sensory Devices:

  • 8 Switches
  • 7 Buttons (up , down, left, right, ok, menu, return)
  • 1 Reset button
  • 8 LEDs
  • 1 4-digit 7 segment display
  • 1 I2c interface (24c02 eeprom)
  • Expansion Connector:

  • 4 gpio connectors (compatible with digilent Pmod)
  • 2 MultiFunction connectors (connect with iMX226 board, or others?
  • Main Chips: xilinx (1.0mm pitch) XC7A100T_FGG676

Interaction and Sensory Devices

  • GPIO Interface  (16 ) 2×8 Standard 2.54mm connector (pin)
  • led output  (8 ) 0603 SMD
  • 8 switchs SMD
  • 7 buttons (Top, Bottom, left, right,center, top left (menu), top right (return)
  • i2c 24c02 smd soic
  • spi flash MX25L6433F 8-SOP (8M bytes)
  • usb2uart ft2232C/H (2 uart ) Or cp2102 (1  uart)
  • jtag 2×5 Standard 2.54mm connectors(pin)
  • eth 1G CAT5 Ethernet (rtl8111e)
  • sram IS61WV25616 (2 pieces ) 256K x 32bit
  • Digital tube 7seg (4) oasistek TOF-5421BMRL-N 
  • Hdmi out adv7511? hdmi_adv7511.SchDoc
  • Test Port? 1×6 Standard2.54mm Connectors ?pin?

isc-V Board Two: FII-PRA040 Altera risc-v SOPC AI Cyclone10

FII-PRA040 Risc-V Educational Platform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Intel Altera.

It was designed for use in all fields of FPGA development and experiments.

Communication

Digital Communication DSP?FPGA?

Network

100M/1G Interface?switch VLAN

USB?

USB2.0 Engine Development

CPU?

RISC-V CPU 32bit Ecosystem Dvelopment and Educational Experiments

Artificial Intelligence

Voice collection, speech recognition Image acquisition and image recognition, deep learning

The Risc-V Learning Tutors for PRX100 Risc-V FPGA Boards:

 

For DPF instruction how to code in Risc-V board, please check the product pages. If you buy one of our products, we will send you detail updated instruction step by step.